1. Technical Field
The present invention relates to a semiconductor memory, and more particularly, to an output enable signal generation circuit of a semiconductor memory.
2. Related Art
A semiconductor memory uses an output enable signal to decide a window of data outputted based on a read operation. The output enable signal is generated within the semiconductor memory and used therein.
FIG. 1 is a block diagram of an output enable signal generation circuit of a conventional semiconductor memory. Referring to FIG. 1, an output enable signal generation circuit 1 of a conventional semiconductor memory includes first to sixth period signal generation units 10 to 60 and a selection unit 70.
The first period generation unit 10 is configured to logically combine a clock signal CLK, a read signal RDR, and a burst signal YBST and generate a period signal OE00.
The read signal RDR is generated using a read command, and the burst signal YBST is generated based on a burst length (BL).
The second period signal generation unit 20 is configured to shift the period signal OEOO based on a clock signal RCLKDLL_OE10 and generate a period signal OE10.
The clock signal RCLKDLL_OE10 is obtained by delaying a delay locked loop (DLL) clock signal RCLKDLL by a preset time.
The third to sixth period signal generation units 30 to 60 are configured to shift period signals OE10 to OE40 based on the DLL clock signal RCLKDLL and generate period signals OE20 to OE50.
The selection section 70 is configured to select one of the period signals OE10 to OE50 based on a CAS latency (CL) and output the selected period signal as an output enable signal OUTEN.
FIG. 2 is a circuit diagram of a first period signal generation unit of FIG. 1. Referring to FIG. 2, the first period signal generation unit 10 includes a plurality of delays DLY1 to DLY3, a plurality of inverters IV1 to IV5, a plurality of NAND gates ND1 and N2, and a plurality of transistors M1 and M2.
The first period signal generation unit 10 enables the period signal OE00 based on the read signal RDR, and disables the period signal OE00 based on a result obtained by logically combining the burst signal YBST and the clock signal CLK.
FIG. 3 is a circuit diagram of a second period signal generation unit of FIG. 2. Referring to FIG. 3, the second period signal generation unit 20 includes a plurality of inverters IV6 to IV9 and a pass gate PG1.
The second period signal generation unit 20 shifts the period signal OE00 based on a clock signal RCLKDLL_OE10 and generates the period signal OE10.
The third to sixth period signal generation units 30 to 60 may be configured in the same manner as the second period signal generation unit 20.
The plurality of delays DLY1 to DLY3 of the first period signal generation unit 10 are configured to secure the timing margins of internal signals for enabling the period signal OE00.
The delay DLY1 secures the margins of the clock signal CLK and the burst signal YBST. Thus, referring to FIG. 4, a high level period of the burst signal YBST should block the clock signal of a burst operation period. Therefore, a falling edge of the burst signal YBST always occurs after the high level period of the clock signal CLK which should be blocked as the delay DLY1 is configured to delay the burst signal YBST.
The delay DLY2 secures the margin of a time point at which the period signal OE00 coincides with the clock signal RCLKDLL_OE10, in order to generate the period signal OE00.
FIGS. 4 to 6 are timing diagrams explaining the operations of a plurality of delays in the conventional semiconductor memory and a problem which occurs therein. Referring to FIG. 5, the read signal RDR may be generated earlier than in FIG. 4, and the burst signal YBST may be much delayed by the delay DLY2. In this case, the delay DLY3 is used to prevent the period signal OE00 from transiting to a low level by a high-level signal DLYOUT although the read signal RDR is inverted by the inverter IV2.
Referring to FIG. 6, however, when the delay time of the second delay DLY2 is set to an excessively large value to secure a margin and the read signal RDR overlaps the low level period of a signal OEBPU (refer to FIG. 2), a rising edge of the period signal OE00 may not be accurately generated or the activation thereof may not occur.
In the above-described output enable signal generation circuit 1 of conventional semiconductor memory, the configuration for controlling the activation and deactivation of the period signal is implemented within one circuit.
Therefore, a trade-off problem occurs in which when a margin for any one of the activation time and deactivation time of the period signal is secured, a margin for the other is reduced. As a result, the clock signal and the operation voltage are limited and degrade the characteristic of circuit operation.